Field emission triode devices have conventionally employed what is often referred to as a “top-gate” or “normal-gate” design, in which in the cathode assembly the gate electrode is located above the electron field emitters, and thus between the cathode electrode itself and the surface of the anode electrode. Within the cathode assembly, the gate and cathode electrodes are electrically isolated with a dielectric insulator layer. As low threshold electron emitting materials such as carbon nanotubes (CNTs) became widely available, such top gate designs in a triode device have become increasingly more attractive for color displays and back light unit applications. Devices with attractive field emission performance have been fabricated using relatively inexpensive thick film process techniques and thick film dielectric and emitter materials.
U.S. Ser. No. 03/141,495 (Lee) and U.S. Ser. No. 05/258,739 (Park) describe top-gate field emission triode devices and methods of fabrication using photoimageable emitting materials and internal thin film UV masks consisting of either metal or amorphous silicon, which must be patterned by costly lithographic steps. Lee discusses extensively the difficulties of avoiding alignment errors when fabricating the cathode assembly for such top-gate triodes due to thermal shrinkage of the substrate between high temperature firing and sequential lithographic patterning steps. He also describes the use of a sacrificial layer in order to avoid residues of emitting material on gate electrode edges caused by an inadequate UV blocking property of the thin film silicon mask layer. Patterning of this sacrificial layer requires an additional lithographic patterning step and is subject to similar alignment error and high cost.
Lee also discloses methods of fabrication of a cathode assembly for such a top-gate triode device using high precision lithographic techniques to achieve accurate alignment of gate and emitter features relative to the center of a via etched in the dielectric layer.
Despite the initial success in device demonstrations, low-cost, high-yield and large-scale fabrication of the cathode assembly for such devices remains a great challenge. Among various technical difficulties, accurate and clean deposition of electron emitting material into dielectric vias while avoiding electrical short circuits between gate and cathode electrodes prove particularly problematic, especially when very large substrates are used. Lee highlights the difficulty of using an internal thin film photomask due to an alignment error caused by substrate shrinkage during firing steps which must take place between lithographic steps for patterning the internal mask, gate holes, dielectric vias, and a sacrificial layer. He also discloses gate and cathode short circuit problems caused by emitter residues occurring at the edge of gate electrodes.
Lee also discloses a solution to the alignment error and residue problem by changing the order in which the internal mask layer and dielectric vias are patterned. Unlike in a conventional method where the internal mask layer is deposited and patterned prior to printing, firing and etching of a dielectric layer, Lee teaches the deposition and patterning of the internal mask layer after the fabrication of dielectric vias. A UV absorptive and electrically resistive thin film layer, such as PECVD grown amorphous silicon, is deposited as the mask layer and patterned. As a result, substrate shrinkage in the cathode assembly does not occur since no firing step is needed between the lithographic patterning of the vias and the mask layer. In addition, the mask layer is deposited on top of the gate electrode and covering the side wall and a portion of the via bottom, thus preventing electrical shorts from being formed by emitter residues contacting both the gate and cathode electrodes. To further assure electrical isolation, a positive-working photoresist, or a negative-working dry film photoresist, is used as a sacrificial layer on the gate electrode surface. During removal of this sacrificial layer, any residue of emitting material that is deposited outside of the via is also lifted off.
To implement Lee's method, several lithographic steps must be accurately aligned. The patterning of the thin film mask layer must be in perfect registration with the via pattern on the substrate. The patterning of the sacrificial layer must also be in perfect registration with the patterned via and mask layer. Since there is no firing between these lithographic steps, perfect registration is achievable in principle. However, as the via size becomes smaller in order to achieve higher resolution and field emission performance, and as the substrate size becomes larger in order to produce large format displays or back light units, as well as to produce multiple panels on a single large substrate to reduce cost, perfect alignment of these lithographic steps can only be achieved at great equipment and processing cost. Any temperature fluctuation across the substrate or photomask surfaces can result in unacceptable alignment error, thus reducing panel performance and production yield. The high investment cost of large area alignment equipment represents a heavy investment burden for low cost devices such as back light units for LCD displays.
A need thus remains for alternative methods to fabricate the cathode assembly in a top-gate triode field emission device to provide ease of manufacturing and reduced final device cost.